One piece semiconductor device having a power fet and a low level signal element with laterally spaced buried layers

ABSTRACT

A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor devices In general and, inparticular, to a composite semiconductor device integrally comprising aninsulated gate (IG) or metal oxide silicon (MOS) field effect transistor(FET) for handling relatively high current and power, and a low levelsignal element of lower current carrying capacity.

The composite semiconductor device has been known which is a one piececonstruction of a power MOS FET and a low level signal element (shown inFIG. 1 of the drawings attached hereto). As heretofore constructed, theMOS FET of the composite semiconductor device was unsatisfactory in itsvoltage withstanding capability. The instant applicant has discoveredthat this drawback is attributable to abrupt bends or transitionsbetween depletion layers created within the device upon application of ahigh voltage. Such abrupt bends are easy to invite field concentrationsand resulting voltage drops.

SUMMARY OF THE INVENTION

The present invention seeks to enable the FET of the compositesemiconductor device of the kind in question to withstand highervoltages than heretofore.

Briefly, the invention may be summarized as a composite semiconductordevice of one piece construction having an insulating gate field effecttransistor and a low level signal element, the latter being less incurrent carrying capacity than the field effect transistor. The devicecomprises a first semiconductor region of a first conductivity type; asecond semiconductor region of a second conductivity type, opposite tothe first conductivity type, which is disposed contiguous to a majorsurface of the first semiconductor region and partly embedded therein; athird semiconductor region of the second conductivity type which islower in impurity concentration than the second semiconductor region,and which is disposed contiguous to the major surface of the firstsemiconductor region, so that the second semiconductor region is buriedin and between the first and the third semiconductor regions; a fourthsemiconductor region of the second conductivity type which is higher inimpurity concentration than the third semiconductor region, and which isformed in the third semiconductor region so as to form a drain of afield effect transistor; a fifth semiconductor region of the firstconductivity type disposed contiguous to the major surface of the firstsemiconductor region and to the third semiconductor region while beingspaced from the second semiconductor region; and a sixth semiconductorregion of the second conductivity type formed in the fifth semiconductorregion so as to form a source of the field effect transistor. Theinvention features at least one additional buried semiconductor regionof the second conductivity type, higher in impurity concentration thanthe third semiconductor region, which is buried in and between the firstand the third semiconductor regions and disposed adjacent the buriedsecond semiconductor region.

Preferably embedded in the first semiconductor region to a depth lessthan the second semiconductor region is, or made less in impurityconcentration than the second semiconductor region, the additionalburied region or regions function to provide more streamlined depletionlayers than heretofore. The power FET will therefore withstand highervoltages.

The above and other objects, features and advantages of this inventionand the manner of realizing them will become more apparent, and theinvention itself will best be understood, from a study of the followingdescription and appended claims, with reference had to the attacheddrawings showing some preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmentary section through the prior art compositesemiconductor device under consideration;

FIG. 2 is a view somewhat similar to FIG. 1 but explanatory inparticular of depletion layers created in the prior art device;

FIG. 3 is a top plan of the improved composite semiconductor deviceconstructed in accordance with the concepts of the present invention;

FIG. 4 is an enlarged, fragmentary section through the improved device,taken substantially along the line A--A in FIG. 3;

FIG. 5 is a view somewhat similar to FIG. 4 but explanatory inparticular of how depletion layers are created in the improved device;

FIG. 6 is a fragmentary sectional view explanatory of a step in thefabrication of buried regions in the improved device;

FIG. 7 a view similar to FIG. 6 but explanatory of another step in thefabrication the buried regions; and

FIG. 8 is a view similar to FIG. 6 but explanatory of still another stepin the fabrication of the buried regions.

DETAILED DESCRIPTION

It is considered essential that the prior art composite semiconductordevice be shown and described in more detail, the better to make clearthe features and advantages of the instant invention. The prior artsemiconductor device shown in FIG. 1, which integrally combines a powerMOS FET and a low level signal element, comprises a p type firstsemiconductor region 1, an n type second semiconductor region or buriedlayer 2, an n type third semiconductor region 3, an n⁺ type fourthsemiconductor region 4 which forms the drain of a power MOS FET, a ptype fifth semiconductor region or channel 5, and an n⁻ type sixthsemiconductor region or source 6. Additionally, the prior art deviceincludes a p type region 7, with n type regions 8 and 9 formed therein,for providing a low level signal semiconductor element or MOS FET.

The first semiconductor region 1 is a substrate. The secondsemiconductor region 2 is formed approximately centrally of a majorsurface of the substrate 1 by impurity diffusion and partly embeddedtherein. Lower in impurity concentration than the second semiconductorregion 2, the third semiconductor region 3 is formed by epitaxial growthon the first semiconductor region 1, thereby burying the secondsemiconductor region 2, and is contiguous to both first and secondsemiconductor regions. Higher in impurity concentration than the thirdsemiconductor region 3, the fourth semiconductor region 4 is formed byimpurity diffusion on the third semiconductor region. The fifthsemiconductor region 5 is formed annularly in the third semiconductorregion 3 by impurity diffusion so as to be exposed on the surface of thesemiconductor chip 10 and contiguous to the first semiconductorregion 1. The sixth semiconductor region 6 is formed annularly In thefifth semiconductor region 5 by impurity diffusion so as to be opposedto the third semiconductor region 3 across part of the fifthsemiconductor region 5.

The regions 7, 8 and 9, which in combination constitute a low levelsignal element, are formed by impurity diffusions In that part of thethird semiconductor region 3 which overlies the buried secondsemiconductor region 2. The low level signal element is herein shown tocomprise only the body 7, source 8 and drain 9, although in practice itmust additionally comprise various other means for driving orcontrolling the power MOS FET, as well as electrodes and insulations.

The power MOS FET of the prior art device is provided with a drainelectrode 11, a ground electrode 12 and a source electrode 13, all ofannular shape, on the semiconductor regions 4, 5 and 6, respectively. Anannular gate electrode 15 is also formed via an insulating film 14 onthat part of the fifth semiconductor region 5 which lies between thirdsemiconductor region 3 and sixth semiconductor region 6.

In order to favorably obtain a field plate effect, and to enable thedevice to withstand higher voltages, a silicon oxide film 16 is providedon that part of the third semiconductor region 3 which lies between thefourth and the fifth semiconductor regions 4 and 5, and on this siliconoxide film there are formed a first metal layer 17 electricallyconnected to the drain electrode 11, a second metal layer 18electrically connected to the ground electrode 12, and one or moreintermediate metal layers 19, 20, 21, 22 and 23. Dielectric layers 24aintervene between first metal layer 17 and intermediate metal layer 23,between second metal layer 18 and intermediate metal layer 19, andbetween the intermediate metal layers 19-23. Consequently, there areobtained a plurality of capacitors which are in serial connectionbetween drain electrode 11 and ground electrode 12.

Upon application of a high voltage between the drain electrode 11 andground electrode 12 of the prior art FET, the pn junction between the ptype first and the n type third semiconductor regions 1 and 3 will bereverse biased, resulting in the creation of a depletion layer, asindicated by the broken line designated 25 in both FIGS. 1 and 2. At thesame time the pn junction 26 between the p type first and the n typesecond semiconductor regions 1 and 2 will also be reverse biased, againresulting in the creation of a depletion layer 27. Although FIG. 1 showsthe depletion layers 25 and 27 as spreading only in the firstsemiconductor region 1, in fact they will spread through the second andthe third semiconductor regions 2 and 3 as well, as indicated in FIG. 2.

The buried second semiconductor layer 2 is intended to prevent thedepletion layer 27 from punching through the third semiconductor region3 to the low level signal element region 7 and so forth. Typically, theimpurity concentration of this second semiconductor region is 6×10¹⁵cm⁻³, which is higher than that of the overlying third semiconductorregion 3. Being formed by impurity diffusion, the second semiconductorregion 2 partly intrudes into the underlying first semiconductor region1, to such an extent that the pn junction 26 is significantly offsetinto the substrate 1 from the pn junction 24. Rather abrupt bends ortransitions 28 have therefore been so far created between the depletionlayers 25 and 27, inviting field concentrations at these transitionsand, in consequence, breakdown.

In order to create the depletion layers 25 and 27 so as to mitigatefield concentrations, it might be contemplated to lower the impurityconcentrations of the p type first semiconductor region 1 and n typesecond and third semiconductor regions 2 and 3. This remedy isunpractical for the following reasons.

First of all, being ordinarily made from of a substrate fabricated bythe familiar Chokralsky method, the first semiconductor region 1 canhave its impurity concentration lowered only to 2.5×10¹⁴ cm⁻³ or so. Afurther reduction in impurity concentration is itself possible withsubstrates made by the known floating zone method. The substrates madeby this second known method are generally so low in oxygen contents,however, that crystal defects are liable to occur in the course of heattreatment conducted during the formation of the buried secondsemiconductor region 2. Excessive reduction in the impurityconcentration of the first semiconductor region 1 is additionallyundesirable by reason of the possibly accompanying parasitic operationof the low level signal semiconductor element. The impurityconcentration of the second semiconductor region cannot be lowered toomuch in order to prevent the punch through noted above. The thirdsemiconductor region 3 takes part in the formation of the low levelsignal semiconductor element, so that its impurity concentration cannotbe lowered so much as to adversely affect the desired characteristics ofthe semiconductor element.

The present invention will now be described in detail in terms of itspreferable embodiment illustrated in FIGS. 3-8. A comparison of FIG. 4with FIG. 1 will best indicate that the illustrated semiconductor deviceaccording to the invention is akin to the prior art device except fortwo additional, floating or buried n type semiconductor regions 31 and32. All the other parts of the inventive device have their counterpartsin the prior art device, so that such parts are designated by the samereference characters as used to denote their counterparts, and theirdescription will be omitted.

Being parts of the power MOS FET, the two additional regions 31 and 32may be referred to as the seventh and the eighth semiconductor regions,respectively, in addition to the six semiconductor regions 1-6 of theMOS FET set forth previously in connection with the illustrated priorart.

As will be noted from FIG. 3, the seventh and the eighth semiconductorregions 31 and 32 are both annular in shape, concentrically surroundingthe buried second semiconductor region 2. Like this second semiconductorregion the regions 31 and 32 are buried between the first and the thirdsemiconductor regions 1 and 3, partly embedded in the first region. Thedepths D₂ and D₃ to which the regions 31 and 32 are embedded in thefirst region 1 are both less than the depth D₁ of embedment of thesecond region 2 in the first region. Further the seventh region 31 isgreater than the eighth region 32 in both cross sectional size and depthof embedment in the first region 1.

In impurity concentration, on the other hand, the two additional regions31 and 32 are less than the second semiconductor region 2 and more thanthe third semiconductor region 3. The typical maximum impurityconcentrations of the three buried semiconductor regions 2, 31 and 32are 6×10¹⁵ cm⁻³, 4×10¹⁵ cm⁻³, and 2×10¹⁵ cm⁻³, respectively, so that theimpurity concentrations become progressively lower in the order of theregions 2, 31 and 32. Incidentally, the third semiconductor region 3 hasan impurity concentration of 1×10¹⁵ cm⁻³.

Such being the improved construction of the composite semiconductordevice according to the invention, the depletion layers 25 and 27 due tothe pn junctions 24 and 26 will be created as in the prior art when avoltage is applied between the drain electrode 11 and the groundelectrode 12 or the source electrode 13 so as to reverse bias the pnjunction 24. At the same time, depletion layers 35 and 36 will also becreated due to a pn junction 33 between p type first region 1 and n typeseventh region 31, and to another pn junction 34 between first regionand n type eighth region 32.

It will be appreciated that the additional depletion layers 35 and 36serve to make smoother the transition between the depletion layers 25and 27, as will be understood from both FIGS. 4 and 5. The transition isso streamlined, indeed, that little or not field concentrations are tooccur. Thus the device will withstanding higher voltages thanheretofore. It is also noteworthy that this objective is accomplishedwithout lowering the impurity concentration of the third semiconductorregion 3. The low level signal semiconductor element, comprised of thesemiconductor regions 7-9, does not therefore suffer from the additionalregions 31 and 32 in any way.

How the additional buried semiconductor regions 31 and 32 are formedwill become apparent from a study of FIGS. 6-8. Before creating theburied second region 2 and epitaxial third region 3, one major surfaceof the first region or substrate 1 may be masked with an oxide film 37,and windows 38, 39 and 40 may be formed in the masking, as illustratedin FIG. 6. The window 38, which is for the creation of the buried layer2, is circular in shape, with a diameter W₁. The two other windows 39and 40 are for the creation of the seventh and the eighth regions 31 and32 and so annular in shape, with widths W₂ and W₃, concentricallysurrounding the central window 38. W₁ >W₂ >W₃.

Then, as Illustrated in FIG. 7, semiconductor regions 2a, 31a and 32amay be formed in the first region 1 by n type impurity diffusion throughthe mask windows 38-40.

Then, with the mask 37 removed, n type silicon may be grown epitaxiallyon the substrate 1 as well as on the regions 2a, 31a and 32a embeddedtherein, thereby forming the third semiconductor region 3 shown in FIG.8. As a result of this epitaxial growth, and of subsequent heattreatment, a partial impurity transfer will occur from the regions 2a,31a and 32a into the third region 3, thereby completing the buriedsecond, seventh and eighth regions 2, 31 and 32 as in FIG. 8. Thesimultaneous creation of the two additional buried regions 31 and 32with the preexisting buried region 2 is preferred because the improveddevice according to the invention can be fabricated almost as quickly asthe prior art device having no buried regions 31 and 32.

Alternatively, the three buried regions 2, 31 and 32 can beprogressively varied in impurity concentration for the creation of evensmoother depletion layers. Typical impurity concentrations in this caseof the second region 2, seven region 31 and eighth region 32 are 6×10¹⁵cm⁻³, 4×10¹⁵ cm⁻³, and 2×10¹⁵ cm⁻³, respectively. The impurityconcentration of the third region 3 may then be 1×10¹⁵ cm⁻³. The threeburied regions 2, 31 and 32 become progressively lower in impurityconcentration in that order. The method of creating such buried regionsof different impurity concentrations is essentially similar to thatdiscussed above with reference to FIGS. 6-8 except that the three buriedregions must be formed one after another, instead of concurrently as inthe foregoing.

This alternative method also makes it possible to make the depths D₁, D₂and D₃ grow less in that order. This feature, combined with theprogressively lowered impurity concentrations of the three buriedregions 2, 31 and 32, results in the creation of streamlined depletionlayers best depicted in FIG. 5. The alternative method is of particularadvantage in cases where the dimensions W₂ and W₃, FIG. 6, aresignificantly greater than the depth of the second region 2.

Despite the foregoing detailed disclosure, it is not desired that thepresent invention be limited by the exact showings of the drawings or bythe description thereof. The following is a brief list of possiblemodifications or alterations of the illustrated embodiments:

1. The three buried regions 2, 31 and 32 could be of the same depth iftheir impurity concentrations were varied as in the alternative method.

2. Only one buried layer could be provided in addition to thepreexisting buried layer 2.

3. Three or more buried layers could be provided in addition to thepreexisting buried layer 2.

4. Two or more additional buried layers could be arranged contiguous toeach other.

5. One or more additional buried layers could be arranged contiguous tothe preexisting buried layer 2.

7. The low level signal semiconductor element could take the form of abipolar transistor.

All such modifications and alterations are intended in the foregoingdisclosure. It is therefore appropriate that the present invention beconstrued broadly and in a manner consistent with the fair meaning orproper scope of the following claims.

What is claimed is:
 1. A composite semiconductor device of one piececonstruction having an insulating gate field effect transistor and a lowlevel signal element, the latter being less in current carrying capacitythan the field effect transistor, comprising:(a) a first semiconductorregion of a first conductivity type having a major surface; (b) a secondsemiconductor region of a second conductivity type opposite to the firstconductivity type, the second semiconductor region being disposedcontiguous to the major surface of the first semiconductor region andpartly embedded therein; (c) a third semiconductor region of the secondconductivity type being lower in impurity concentration than the secondsemiconductor region, the third semiconductor region being disposedcontiguous to the major surface of the first semiconductor regionthereby burying the second semiconductor region in and between the firstand the third semiconductor regions; (d) a fourth semiconductor regionof the second conductivity type being higher in impurity concentrationthan the third semiconductor region, the fourth semiconductor regionbeing formed in the third semiconductor region so as to form a drain ofa field effect transistor; (e) a fifth semiconductor region of the firstconductivity type disposed contiguous to the major surface of the firstsemiconductor region and to the third semiconductor region while beingspaced from the second semiconductor region; (f) a sixth semiconductorregion of the second conductivity type formed in the fifth semiconductorregion so as to form a source of the field effect transistor; (g) anadditional buried semiconductor region of the second conductivity typebeing higher in impurity concentration than the third semiconductorregion, the additional buried semiconductor region being buried in andbetween the first and the third semiconductor regions and disposedadjacent the buried second semiconductor region; (h) a drain electrodeformed on the fourth semiconductor region; (i) a source electrode formedon the sixth semiconductor region; (j) a gate electrode formed on thefifth semiconductor region via an insulating film; (k) a groundelectrode formed on the fifth semiconductor region; and (l) a low levelsignal element formed in the third semiconductor region.
 2. Thecomposite semiconductor device of claim 1 wherein the additional buriedsemiconductor region is embedded in the first semiconductor region to adepth less than the second semiconductor region is.
 3. The compositesemiconductor device of claim 1 wherein the additional buriedsemiconductor region is less in impurity concentration than the secondsemiconductor region.
 4. The composite semiconductor device of claim 1further comprising a second additional buried semiconductor region ofthe second conductivity type being higher impurity concentration thanthe third semiconductor region, the second additional buriedsemiconductor region being buried in and between the first and the thirdsemiconductor regions and disposed farther away from the secondsemiconductor region than is the first recited additional buriedsemiconductor region.
 5. The composite semiconductor device of claim 4wherein the second additional buried semiconductor region is embedded inthe first semiconductor region to a depth less than the first additionalburied semiconductor region is.
 6. The composite semiconductor device ofclaim 4 wherein the second additional buried semiconductor region isless impurity concentration than the first additional buriedsemiconductor region.
 7. The composite semiconductor device of claim 1further comprising:(a) an oxide film formed on the third semiconductorregion; (b) a first conductive layer formed on the oxide film andelectrically connected to the drain electrode; (c) a second conductivelayer formed on the oxide film and electrically connected to the groundelectrode; (d) at least one intermediate conductive layer formed on theoxide film and disposed intermediate the first and the second conductivelayers; and (e) a plurality of dielectric layers disposed intermediatethe first conductive layer and the intermediate conductive layer andintermediate the second conductive layer and the intermediate conductivelayer.
 8. The composite semiconductor device of claim 7 wherein each ofthe first and the second conductive layers, and the intermediatconductive layer is a metal layer.